博士论文答辩：面向数字电路的晶体管级到门级的先进综合及分析方法
日期：2024/05/22 - 2024/05/22
博士论文答辩：面向数字电路的晶体管级到门级的先进综合及分析方法
主讲人：Weihua Xiao, Ph.D. candidate at UM-SJTU Joint Institute
时间：2024年5月22日（周三）上午10:00
地点：龙宾楼414B会议室
讲座摘要
Digital circuit synthesis and analysis from transistor level to gate level play crucial roles in the development of very large-scale integrated (VLSI) circuits. The purpose of synthesis is to achieve an optimized representation for implementing the Boolean function of a specified digital circuit, with a primary focus on minimizing its hardware cost, while the purpose of analysis is to determine the various forms of hardware cost, including area, delay, and power. However, as VLSI designs become increasingly complex and transistors approach their physical limit, traditional synthesis and analysis techniques for digital circuits are faced with difficulty in further enhancing circuit performance and energy efficiency. At the aspect of the transistor-level synthesis, traditional techniques cannot generate the optimal transistor networks with fewest transistors for implementing desired Boolean functions. At the aspect of the gate-level synthesis, it includes the exact and approximate gate-level synthesis. The exact gate-level synthesis of digital multipliers, which have widespread applications in many fields, is of great importance, but traditional synthesis techniques cannot globally optimize multipliers, leading to sub-optimal designs. Additionally, the approximate gate-level synthesis, significant to an emerging computing paradigm called approximate computing for creating highly energy-efficient systems, introduces complexities in balancing hardware cost reduction with the minimization of introduced error, and requires more systematic exploration. Finally, the gate-level probability analysis is a key problem in many circuit analysis tasks, such as the dynamic power estimation and the reliability analysis. However, traditional works struggle to make a good trade-off between the accuracy and efficiency of the probability analysis. This dissertation focuses on tackling the above challenges to advance the digital circuit synthesis and analysis from transistor level to gate level.
主讲人简介
Weihua Xiao received the B.S. in communication engineering from Xidian University in 2019. He is currently a Ph.D. candidate at the UM-SJTU Joint Institute, supervised by Prof. Weikang Qian. His current research interests include electronic design automation algorithm, logic synthesis, approximate computing.