High-Density Memory and In-Memory Computing based on Resistive Switching Devices towards High Energy Efficiency

Date: 2025/01/16 - 2025/01/16

Dissertation Title: High-Density Memory and In-Memory Computing based on Resistive Switching Devices towards High Energy Efficiency

Speaker: Yueyang Jia, Ph.D. candidate at UM-SJTU Joint Institute

Time: January 16 from 10:30 a.m., 2025 (Beijing Time)

Location: Room 414B, Longbin Building

Abstract

In the big data era, there is an increasing demand for high-density data storage and energy-efficient computing. The lateral dimension scaling of complementary-metal-oxide-semiconductor (CMOS) has been slowing down, while off-chip dynamic random-access memory (DRAM) usually incurs long latency and high energy consumption. It is challenging for the conventional von Neumann architecture to satisfy the increasing speed of data processing because of its limited data transfer bandwidth between the memory unit and the computing unit, which is also known as the “memory wall” problem.

Technologies like the Hybrid Memory Cube and High Bandwidth Memory have emerged to meet the demand for faster data transfer and increased memory density, by utilizing three-dimensional stacking of memory chips interconnected by through-silicon vias (TSVs). However, challenges persist in the implementation of these solutions. Advanced packaging techniques, such as 2.5-dimensional silicon interposers and die stacking, are being actively explored to achieve greater integration density within packages. Nevertheless, this integration relies heavily on costly TSVs, which often suffer from large pitch, low yield, and reliability issues. Therefore, novel memory devices that are integration-friendly, high-density, and low-power are necessary, and emerging computing architectures such as in-memory computing devices are promising for enabling higher energy efficiency.

Toward this goal, in this thesis, the author focuses on the study of emerging non-volatile memory devices and their monolithic three-dimensional (3D) integration, for the applications in high-density memory and in-memory computing systems. Firstly, the author systematically studies the physical principles of resistive switching devices. The author develops a consistent compact model for bipolar/unipolar resistive random-access memories (RRAMs), which can comprehensively explain the gradual/abrupt and many abnormal phenomena during the switching processes. The model provides a deep understanding of the resistive switching phenomena and a platform for tuning RRAM properties and circuit simulations toward memory and computing applications.

Secondly, the author demonstrates the high-density memory and its applications for in-memory computing based on the monolithic 3D integrated systems. The integrated system is formed by the transistors and 3D vertical RRAMs (VRRAMs) fabricated at low temperature and 3D RRAMs, interconnected by inter-layer vias, forming 1T-nR structure. The n layers of RRAMs could be programmed simultaneously, showing high feasibility for parallel operation. Based on the measurement data, fitting is performed based on model for extracting important device parameters. Circuit-level simulation results show that the monolithic 3D integrated 1T-nR system can highly reduce the area, latency and power compared with the conventional planar structure, due to the reduced lateral signal transmission path. The author then demonstrates the in-memory logic operations based on the 1T-nR system, showing seamless integration of memory and logic functions.

Finally, aimed at further improving the ON/OFF resistance ratio, multi-bit property and the repeatability, the author demonstrates the optimization of memory devices by leveraging the properties of ferroelectric materials. The ferroelectric tunnel junctions (FTJs) show giant ON/OFF resistance ratio with a nanometer-scale ferroelectric layer, and achieve more than 32 distinct resistance levels corresponding to 5 bits of data storage. The author then demonstrates in-memory search with the 2R based Ternary Content-Addressable Memory (TCAM) for highly-parall data search. The TCAMs based on FTJs with giant ON/OFF ratios can highly reduce the area and complexity compared with 2T2R based TCAM. The results show that the resistive switching devices are promising candidates for future high-density memory and energy-efficient computing systems.